The present invention relates to Flash memory, and more particularly, this invention relates to background threshold voltage shifting using base and delta threshold voltage shift values in Flash memory.
The residual bit error rate (RBER) of a Flash memory block will typically increase over time due to additional program and erase cycling, charge leakage from retention, and additional charge placed in the cells by read operations (i.e., read disturb errors). Typically, a Flash memory block is retired when any page in the block exhibits a code word that reaches a page retirement error count limit. This limit is typically set to be achieved in conjunction with an appropriate error correction code (ECC), with the RBER for a Flash memory block being set to be similar to the RBER in traditional hard disk drives, e.g., at around 10×10−15, but may be more or less.
Threshold voltage shifting, also known as block calibration, has been shown to be a key contributor to enhance endurance and retention for enterprise-level Flash memory systems using 19 nm and sub-19 nm NAND Flash memory. Preferably, the optimal threshold voltage shift values are determined shortly after a Flash memory block has been written. Unfortunately, this is not possible under a sustained heavy write workload without impacting data path performance. After initial writing, the threshold voltage shift values should be updated periodically as long as data remains on the Flash memory blocks. However, this would require significant additional read workload and data processing for every Flash memory block written, which is not acceptable in a Flash memory system.
Therefore, block calibration must be executed fully in the background and not in the data path. Executing Flash memory block calibration in this way, however, may result in some Flash memory blocks not being accurately calibrated. Those Flash memory blocks will exhibit a significantly higher RBER, which may result in unnecessary uncorrectable read errors or early and unwarranted Flash memory block retirement.